Scalable AI-driven inspection for inline nuisance filtering and whole wafer pattern classification

Yield optimization is a driving factor for competitiveness in semiconductor manufacturing, where even subtle inspection inefficiencies can impact profitability. Conventional ADC workflows rely on extensive manual image review. This creates bottlenecks, produces inconsistent results, and inflates defect counts due to optical artifacts. This paper introduces a unified ADC Total Solution developed by Onto Innovation that integrates three complementary modules: In-line ADC+, Post Micro ADC, and Post Whole Wafer ADC (Macro ADC). Unlike approaches that aim to replace human review, this solution strategically applies AI at specific inspection bottlenecks to enhance rule-based detection. The In-line ADC+ module applies a lightweight binary (0/1) segmentation model for real-time nuisance filtering during AOI, while Macro ADC performs wafer-level pattern recognition for process-level insights. Together with Micro ADC, these components create a fully automated, end-to-end inspection and classification ecosystem. Deployed across High-Volume Manufacturing (HVM) environments, the solution demonstrated significant reduction of nuisance defects (up to 95%), achieved 100% wafer-level pattern classification accuracy, and minimized operator dependence. This integration delivers greater consistency, throughput, and scalability while preserving the precision of rule-based inspection.