Ring-type shape laser beam processing for Si wafer release by laser lift-off (LLO) and thermal damage characterization

Advancements in semiconductor packaging are critical for the improvements in high-bandwidth memory (HBM) and artificial intelligence (AI) applications. Laser lift-off (LLO) uses a short-pulsed IR laser beam to form a thermal stress to release fusion bonded Si wafers at a targeted interface. The laser beam was focused above the release stack layer by ftheta lens and scanning galvo to achieve the uniform thermal stress for release. A focused Gaussian beam mode resulted in the released wafer surface with total thickness variation (TTV) greater than 100 nm, which effected subsequent reuses. The defocused ring-shaped laser beam built by Vortex lens revealed a smoother surface within the acceptable range to be rebuilt after LLO. The ring-shaped mode resulted in through-put increase to contribute for cost reduction and environmental sustainability of the LLO process. However, LLO may generate the thermal and mechanical stresses during LLO that could affect on the device (CFET, NAND, and other memory cells) integrity.

We investigated the thermal damage mechanisms and mitigation strategies for stacked structures during carrier wafer release. Metal silicide phase transitions were characterized by X-ray diffraction (XRD) to detect less than 500 °C exposure. These measurements were calibrated against rapid thermal annealing (RTA) references to establish a thermal budget for LLO exposed devices.

The results of these thermal damage experiments were used to model a broader spectrum of stacked materials. The absorption through the stack and the resulting heat transfer were simulated. Since experimental measurements generally require orders of magnitude for longer timescales than laser exposure, it is challenging to compare the energy spike in LLO simulation to a thermal budget based on RTA processing. If for a given stack it has been demonstrated experimentally that the heat energy from the laser is at an acceptable level, then it is reasonable to assume that other stacks that show equal or less heat energy in simulation are also acceptable. This combined experimental–simulation framework enables optimized stack engineering, ensuring device integrity and sustainable wafer reuse in advanced packaging.