Paper 14040-8
DARSoC: a radiation-hardened reconfigurable LiDAR SoC for long-range atmospheric sensing
29 April 2026 • 2:30 PM - 2:50 PM EDT | Chesapeake 5
Abstract
This paper presents a light detection and ranging (LiDAR) system on a chip (DARSoC), an 8 channel, radiation hardened by design (RHBD), long-range, direct time-of-flight (dToF) application specific integrated circuit (ASIC) for long-range sensing from airborne and spaceborne platforms. Space based LiDAR systems are constrained by strict size, weight, and power (SWaP) requirements. Furthermore, they must be radiation tolerant and include sufficient onboard processing to reduce downlink throughput. DARSoC contains a complete LiDAR signal chain per channel, including an analog front-end (AFE), timing and control logic with time-over-threshold (ToT) amplitude estimation, and a digital back-end (DBE) for on-chip histogram processing and data transmission, all within a single RHBD ASIC implemented in a 65 nm technology. To support a wide array of long-range sensing applications, DARSoC can be configured for varying signal levels, range regions, and detector types. The DARSoC AFE is compatible with both Geiger mode (GM) and linear mode (LM) avalanche photodiodes (APDs) and provides configurable gain per channel, enabling over 120 dB of dynamic range when aggregated across channels. Furthermore, timing and control logic supports region of interest (ROI) selection, allowing different range selections per channel to target specific regions and enable simultaneous observation of multiple range layers, which are then processed by the histogramming logic to construct vertical profiles. The histogram logic can average a full vertical profile and up to 255 horizontal profiles. DARSoC combines multi-mode APD support, over 120 dB of dynamic range, long-range timing and control logic, and on-chip histogramming within a single RHBD LiDAR SoC for long-range sensing. DARSoC has been successfully fabricated, packaged, and characterized, demonstrating AFE gain reconfigurability, < 410 fA/√Hz input-referred noise for linear mode operation, 45 ps TDC resolution, 120 dB of aggregate dynamic range, < 30 mW per channel power consumption, and configurable timing and control, including region of interest selection and on-chip histogramming.
Presenter
Megan Manifold
SenseICs (United States)
Megan Manifold is a Design Engineer at SenseICs Corporation, where she has contributed since 2020 to a range of advanced sensor technologies, including frame timer solutions for high dynamic range (HDR) and asynchronous handshaking interfaces for event-based image sensors, as well as advanced node cryptography cores. She received her B.S. and M.S. degrees in Electrical and Computer Engineering from The Ohio State University in 2019 and 2020, respectively.