This PDF file contains the front matter associated with SPIE Proceedings Volume 13902, including the Title Page, Copyright information, Table of Contents, and Conference Committee information.

Monolithic III–V-on-silicon light sources are a key missing element for scalable silicon photonic integrated circuits. This talk presents a pocket-heteroepitaxy platform that directly grows InAs quantum-dot gain on 300-mm foundry silicon photonic wafers and enables efficient butt-coupling to Si/SiN waveguides. We first show electrically pumped Fabry–Pérot pocket lasers with CW operation up to 60 °C, 126.6 mW double-side output at 20 °C, and 8.6% wall-plug efficiency. We then address the dominant integration bottleneck—laser-to-waveguide coupling—via (i) two-step MOCVD+MBE growth plus polymer facet gap-fill, achieving single-mode DBR/ring-stabilized O-band lasing with up to 32 dB SMSR, operation to 105 °C, and multi-year projected lifetime; and (ii) selective-area MBE buffers that suppress polycrystalline sidewall growth, shrinking the air gap and reducing coupling loss from 12.05 dB to 9.07 dB. Together, these results outline a manufacturable path to wafer-scale, high-temperature, low-loss on-chip lasers for advanced silicon photonics.

Driven by growing demands in applications such as high-bandwidth optical interconnects and LiDAR systems, achieving high on-chip optical power without compromising efficiency, reliability, and noise of light sources remains a key challenge in silicon photonics.

In this work, we present the design, fabrication, and characterization of a heterogeneously integrated, high-power, single-wavelength light source on a 300 mm silicon photonics platform, delivering over 100 mW of output power. The device employs an on-chip coherent beam combining (CBC) scheme, where light from a master distributed feedback (DFB) laser is amplified by two following semiconductor optical amplifiers (SOAs) and coherently combined into a single mode silicon waveguide. Both the on-chip DFB and SOA sections are realized by directly bonding III/V multiple quantum well (MQW) gain materials onto pre-patterned silicon waveguides, with a tapered mode converter enabling low-loss evanescent coupling to the silicon photonic integrated circuits.

Under continuous-wave (CW) operation, the coherently combined laser achieves stable single mode operation with a >100 mW on-chip output power while maintaining a narrow intrinsic linewidth of 31.4 kHz, a high side-mode suppression ratio (SMSR) greater than 50 dB, and a relative intensity noise (RIN) less than -145 dBc/Hz.

In this work, we demonstrate an all-silicon thermo-optic tunable micro-ring modulator using AIM Photonics’ 300 mm process technology. We used silicon on insulator (SOI) technology to define our waveguides and create our heater elements. The modulator includes a 7-μm-radius silicon ring waveguide and a silicon straight waveguide outside the ring, with a coupling gap. The rib height and width of the modulator are 110 nm and 1 μm, respectively. The 1-μm-wide rib is attached to a full-height silicon of approximately 1 μm width for modulator contact regions. The heater element is positioned after the modulator contact regions and a voltage of up to 8 V is applied to the heater to thermally tune these devices. The modulator heater performance is tested by measuring the resonance shift of the modulators with and without introducing trenches outside the devices. A non-trenched modulator reported to shift the resonance of approximately 1.7 nm at the applied voltages of 8V, while the same applied voltages shift the resonances of approximately 13.7 nm with the trenched modulator. The trenches are expected to trap heat within the device areas, while the non-trenched modulator spreads it outside the device, reducing thermal tuning efficiency. It is noted that the trenched devices are eight times more thermally efficient in tuning the resonances than the non-trenched traditional thermally tunable modulators.

We demonstrate a separate absorption, charge and multiplication (SACM) avalanche photodiode (APD) on silicon nitride (Si₃N₄) waveguide using an adhesive die-to-wafer bonding technique. Our heterogeneous APDs have a low dark current of 10 nA at -27 V. A 120 μm long APD has 77% internal quantum efficiency at unity gain, and a responsivity of 14 A/W at -29 V for -11.9 dBm input optical power at 1550 nm wavelength.

Germanium (Ge) epitaxy plays a critical role in silicon photonic circuit manufacturing, particularly for high-performance waveguide photodiodes where precise control of epitaxial thickness is required to achieve target cut-off frequency and responsivity [1, 2]. However, thickness control and wafer-level uniformity in epitaxial growth processes are governed by complex, nonlinear interactions between multiple process parameters, rendering conventional trial-and-error and heuristic-based optimization approaches inefficient and costly. In this work, we present a data-efficient, AI-driven optimization framework for Ge epitaxial thickness control based on Gaussian Process Regression (GPR) and Bayesian Optimization (BO). The GPR surrogate model accurately predicts Ge thickness with an R² score of 0.89 and a mean absolute percentage error (MAPE) of 6.7%, while providing calibrated uncertainty estimates. Bayesian Optimization using the Expected Improvement (EI) acquisition function is employed to iteratively propose new experimental conditions that minimize both the mean thickness error relative to target and wafer-level thickness variance. The proposed approach achieves a best non-uniformity of 1.09% while significantly reducing the number of experimental runs compared to conventional design-of-experiments (DOE) methods. This work demonstrates the effectiveness of integrating probabilistic machine learning with process engineering to accelerate epitaxial process development and enable scalable, data-efficient semiconductor manufacturing optimization.

Photonic Integrated Circuit (PIC) microchip-based optical gyroscopes continue to develop as promising contenders for use in high-precision Inertial Measurement Unit (IMU) applications. With the advancement in heterogeneous materials integration, PIC chip-based gyroscopes can offer IMUs with much better SWaP-C (Size, Weight, Power, and Cost) characteristics in comparison to the more costly Fiber Optic Gyroscope (FOG) units. OSCPS Motion Sensing Inc. (d.b.a. OSCP) has designed and developed patented photonic chips for use in optical gyroscopes, with both interferometric spiral-based and resonant ring-based PIC microchips exploiting the Sagnac effect. The electro-optical performance of the PIC chip-based gyroscope has been shown to be competitive with tactical-grade FOGs. In this paper, we report on a Thin Film Lithium Niobate (TFLN)-based phase modulator PIC chip as a viable candidate for an all-chip photonic gyroscope, providing design features, and characterization of V_π, as well as the measured modulation frequency. Given these characteristics, the optical gyroscope module has been shown to be a viable candidate for high-precision gyroscopes for autonomous vehicle, drone, and industrial robotics applications.

A photonic metamaterial emitter generates ≈300 μm optical beams at 460 nm with user defined polarization, intensity, and phase. By superimposing weak, continuously varying perturbations onto a translation symmetric slab metamaterial, an incident TE slab mode is converted into outputs with smooth intensity profiles spanning TE, TM, diagonal linear, and circular polarization states.

AI computing systems, warehouse robots, and autonomous drones all require unprecedented data movement bandwidth, low latency, and reconfigurable connectivity. Copper interconnects, mmWave radios, and fiber-based optical networks face fundamental scaling limits in bandwidth density, power efficiency, and topology rigidity. OTenna is a CMOS-compatible free-space optical phased array (OPA) technology that forms electronically steerable light beams for terabit-class point-to-point links without fibers or mechanical beam steering. Using leaky-wave silicon photonics with liquid-crystal phase tuning, OTenna supports 2D beam steering, multi-beam parallelism, and reconfigurable topologies. We present OTenna as a unifying optical fabric for two high-impact applications: (1) chip-to-chip communication in AI server packages, enabling > 50 Tb/s per package with sub-pJ/ bit energy efficiency, and (2) machine-to-machine (M2M) networking among autonomous robots and drones, enabling secure, interference-free, and scalable optical meshes. This paper describes the device architecture, free-space link design, system integration, and application-level benefits for both domains.

Through silicon vias (TSVs) are key enablers of the next generation of microelectronic products. TSVs are holes through the silicon substrate, filled with a metal, forming vertical conductors between the backside and the frontside of the die. In the last 10 years, TSV dimensions have been strongly decreased, and their diameters are now reaching sub-micrometer dimensions, with aspect ratios just below 10. In this article, multiple sources of reliability concerns will be reviewed. First of all, the reliability of the liner/barrier system will be addressed. The difficulty to obtain full sidewall coverage, due to high aspect ratios, small via diameters or etch topography, and its impact on reliability will be demonstrated. Furthermore, the need to optimize the etch recipe to avoid copper sputtering leading to poisoning of the liner will be clarified. Finally, the electromigration performance of the TSVs will be discussed.

CORNERSTONE is a UK-based open-source silicon photonics fabrication platform designed to accelerate research, development, and commercialisation in integrated photonics. Our mission is to realise a continuous pipeline of silicon photonics-enabled technologies and companies that can serve a wide range of global industries by 2030. We accelerate innovation by bringing together tailored start-up support, engaging networking events, expert design consultancy, and flexible prototyping, backed by our open-source silicon photonics foundry. We support innovation through multi-project wafer runs, bespoke process development, and comprehensive design-to-fabrication guidance. This talk will highlight how CORNERSTONE fosters collaboration, reduces development risk, and bridges the gap between concept and scalable manufacturing. It will share the latest results from our team and our partners in a variety of approaches to modulation in silicon photonics technologies.

Silicon photonics (SiPh) have gained renewed attention due to applications like co-packaged optics (CPO) for AI datacenters. As photonic integrated circuits (PIC) move toward high-volume manufacturing, focus is shifting to performance, reliability and wafer-scale manufacturability. The performance of components such as micro-ring modulators (MRM) and SOI waveguides depends critically on factors such as epi silicon thickness, etch depth, width, sidewall angle, line edge roughness, refractive index variation, and defectivity. This work examines how inline wafer-scale manufacturing process variations affect PIC performance, in particular energy consumption, highlighting implications for metrology, inspection and process control. Power consumption is a key limiter for AI data center growth.

We present a manufacturing-aware adjoint-based shape optimization methodology for silicon photonic devices that incorporates design rule checking (DRC) directly into the optimization loop. The DRC engine is treated as a black-box feasibility oracle, and a two-stage update filter combines a global line search with greedy coordinate backtracking so that only DRC-compliant iterates are accepted. We apply the method to a dual-layer silicon/silicon-nitride focused grating coupler and achieve a coupling loss of 3.88 dB, improving by 1.14 dB over a uniform-width baseline, while satisfying foundry rules throughout the optimization and avoiding post-optimization legalization.

Integrated Brillouin photonics has experienced rapid progress in recent years. In this talk, I will discuss our work regarding harnessing and utilizing stimulated Brillouin scattering signals in scalable integrated photonic platforms, with special focus on thin-film lithium niobate and tellurite-covered silicon nitride. Moreover, I will discuss stimulated Brillouin laser and Brillouin microwave photonic filters in these two platforms.

Silicon (Si) photonic integrated circuits (PICs) allow for the combination of high-speed Si electronics with integrated photonic components on a single chip. However, integrated photonic modulator designs are often limited by the driving electronics since, modulators often require large voltage swings from high-speed electrical driving circuits. Due to inherent gain-bandwidth trade-offs, creating high-speed voltage drivers with large voltage swings is difficult without considerable design effort. The use of Ring-assisted Mach-Zehnder Modulator (RA-MZM) schema allows for compact modulator design while decreasing Vπ, resulting in less restrictive driving voltage requirements. Electronic requirements can be further reduced by employing a single-ended push-pull scheme for the RA-MZMs and exploiting intentionally over- and under-coupled RA-MZM designs targeting phase or amplitude cancellation operation. RA-MZM design optimization allows for more lenient voltage swing design requirements at the electronic-photonic interface, facilitating modulation at higher speeds while still preserving data fidelity.

Reconstructive spectroscopy is an emerging technique that facilitates the development of miniaturized sensors for lab-on-chip technologies. Numerous works on reconstructive spectrometers have been demonstrated (utilizing narrowband filters, meta-structures, quantum dots, photonic crystals, etc.) that provide high performance spectroscopy in a compact form-factor. A common trade-off for this technology is the spectral range versus spectral resolution. This becomes crucially important when reconstructing narrow-band spectra, such as lasers, over a broad spectral range for LiDAR applications. In this paper, we present an AI-assisted method for hyperspectral imaging that can achieve a spectral linewidth (FWHM) of <4 nm, approximately 3× better than conventional algorithms. Specifically, we implement a custom loss function combining Root Mean Squared Error (RMSE) and Pearson’s correlation coefficient that significantly improves the accuracy and convergence of neural networks for narrow-band spectra reconstruction. We experimentally validate the results using an on-chip silicon spectrometer with an ultra-broadband spectral range of 640–1100 nm, achieving narrow spectral features of 3.6 nm on average with ∼100% peak accuracy. The spectrometer utilizes 16 unique silicon photodiodes enhanced with photon-trapping nanostructures that enable spectral engineering in a CMOS-compatible platform. These results open up possibilities for on-chip, low-cost silicon spectrometers for scientific, communication, biomedical, and consumer applications.

PureB Ge-on-Si photodiodes were fabricated on silicon wafers highly-doped (HD) with arsenic to more than 10¹⁹ cm⁻³. As compared to diodes previously fabricated on wafers lightly-doped (LD) with phosphorus to 10¹⁵ cm⁻³, the operation voltage was shifted from a high reverse bias of 15 to 20 V to the 0 to 2 V region. The Ge was grown at 700 °C by chemical-vapor deposition to selectively fill windows in 3.5-μm-thick oxide. They were capped in-situ, also at 700 °C, with a 10-nm-thick pure boron layer to form the p-type anode region. Near-ideal responsivities of 0.21, 0.28, 0.64, and 0.57 A/W were obtained at 406, 670, 1310 and 1550 nm wavelengths respectively, in spite of relatively high defect densities related to a significant degree of arsenic autodoping. For the first, the high arsenic concentration at the Ge-Si interface eliminated the influence of a p-type interfacial potential barrier that otherwise impeded the detection of photogenerated carriers in photodiodes fabricated on LD substrates. In addition, the arsenic autodoping of the Ge resulted in a doping gradient and associated electric field that aided in the separation and detection of carriers photogenerated in the non-depleted Ge.

Development of a Dolmen plasmonic resonator to work as a water quality sensor has been reported. We have conducted a comprehensive study on the Fano characteristics of gold deposited on silicon nano dolmen structure, achieving continuous manipulation of the Fano resonances in the near-infrared region. This metasurface sensor presents a promising platform for diverse applications, including gas and biological sensing, and security. Furthermore, an investigation into the fabrication tolerance was conducted to validate the sensor's reliability. The measured refractive index sensitivity, evaluated from 1.33 to 1.34, corresponds to the typical range induced by common impurities in water. The sensor achieves a sensitivity of 1288 nm/RIU

Mid-infrared detection technology has critical applications in autonomous vehicles, thermal imaging, body temperature measurement, and military areas. Currently, most optical detectors rely on III-V compound semiconductors. Despite their high performance, the manufacturing process is complex and costly; furthermore, they are difficult to integrate with silicon-based integrated circuits. In this study, we fabricated a silicon-based detector with a lateral size of 0.3 cm, incorporating a periodic inverted pyramid structure (IPS) to induce strong surface plasmon resonance, which significantly enhances the detection of blackbody radiation within the human body temperature range. Two types of metal–semiconductor junctions were investigated: Ag/n-type and Cu/p-type. For the Ag/n-type device, a temperature resolution of 0.5 °C was achieved. At 35 °C and under a reverse bias of 0.3 V, the response current slope reached 0.00203 μA/s, increasing linearly in steps of 0.2 °C, and reaching 0.0049 μA/s at 42 °C. In contrast, the Cu/p-type device demonstrated a higher sensitivity with a resolution of 0.2 °C. At 35 °C, the response current slope was 0.771 μA/s, increasing linearly with a 0.2 °C step size to 4.725 μA/s at 42 °C. This research demonstrates the potential of silicon-based detectors, enhanced by plasmonic structures, for precise and cost-effective human body temperature monitoring, highlighting their value for practical applications in healthcare and sensing technologies.

This report describes the experimental demonstration of a silicon-nanowire-based flat-topped demultiplexer, specifically designed for Long Reach 8 (LR-8) wavelength-division multiplexing targeting 400 GbE interconnects. The motivation stems from the limitations of conventional bulk and silica-based demultiplexers. The proposed device is based on a multi-stage, multiple delayed interferometric (MDI) structure. Its core consists of four MDI stages, featuring precisely engineered optical path differences and multimode interference (MMI) couplers with varied splitting ratios. The third stage incorporates an intentionally shortened path difference to disrupt spectral periodicity. To further enhance band suppression ratio and ensure flat-topped responses, additional band rejection filters are introduced in the fourth stage. The device achieves an ultra-compact footprint of 600 × 300 μm² and employs passive silicon waveguides (220 nm thick, 410 nm wide). The measured discrete, non-uniformly spaced channel grid in the O-band closely aligns with theoretical simulations based on coupled mode theory. A measured band suppression of 11 dB and box-like spectral shapes validate the design, with minor distortions attributed to fabrication-induced phase errors. This study also experimentally confirms the impact of statistical excess phase errors by evaluating an alternative waveguide design with a width of 350 nm. Importantly, the non-periodic, flat-topped LR-8 spectral characteristics were successfully demonstrated under TE-polarized input. The report also discusses performance limitations such as spectral crosstalk and suboptimal suppression ratio, identifying phase imbalance in certain asymmetric MMI couplers as the main cause. These degradations can be mitigated by integrating discrete phase shifters in the third MDI stage, without adding design or fabrication complexity. This work sets a new benchmark for integrated LR-8 demultiplexer designs, combining spectral flatness, non-periodicity, compactness, and thermal stability - key features for next-generation high-capacity interconnects.

We demonstrate a thermally reconfigurable broadband silicon photonic coupler/splitter based on deep photonic network architecture that overcomes wavelength-dependent tunability limitations in conventional devices. The device employs 8 cascaded Mach–Zehnder interferometer layers (700 μm total length) with 30 thermally controlled arms and custom waveguide tapers. Using automatic differentiation-based optimization, thermally tuned taper geometries achieve arbitrary optical transfer functions. The structure dynamically reconfigures post-fabrication to multiple power splitting ratios (0-100% through 100-0% in 10% increments) with < 2% deviation from target across the 1.5-1.6 μm wavelength range. This represents the first thermally tunable ultra-broadband splitter design in a fully silicon-based architecture, eliminating the need for dedicated layouts for each splitting ratio or optical function. The approach enables universally programmable broadband silicon photonics, offering significant advantages for communications, computing, and sensing applications requiring wavelength-agnostic reconfigurable optical functionality.

In this work, we demonstrate an increase in the thermo-optic coefficient for silicon of approximately 20% through a low-dose, 70keV Si⁺ implantation modification of an SOI structure. The thermo-optic effect is quantified using temperature-dependent spectroscopic ellipsometry, extracting the optical constants of the material as heated.

With low propagation losses and good thermal stability, Silicon Nitride (SiN) is major building block of photonic circuits to tackle the requirements of data-rate increase and low energy consumption, driven by artificial intelligence applications. In this work, stoichiometric sputtered Si₃N₄ layers were first integrated leading to losses of 3 dB/cm in C-band (1550 nm). Gas flows of Ar/N₂ were optimized to tailor Si_xN_y composition and develop silicon enriched layers with a refractive index above 2 at 1550 nm. Through material engineering and waveguide fabrication optimization, optical losses as low as 0.30 dB/cm in the O-band (1310 nm) and 0.17 dB/cm in the C-band have been achieved.

Near-infrared (NIR) spectroscopy is widely used in agriculture and in industry. However, conventional NIR spectrometers use a costly detector and require a large size for sufficient performance, limiting their use in consumer products. To address this, we are developing a novel NIR spectroscopic sensor based on surface plasmon resonance (SPR) using a gold-coated diffraction grating on n-type silicon. The sensor operates by detecting photocurrent generated when SPR-excited electrons in the gold film overcome the Schottky barrier at the gold–silicon interface. A key feature of this system is that the SPR excitation wavelength depends on the incident angle of light. In earlier designs, we explored a cantilever-based sensor that could mechanically vary the incident angle using electrical actuation. However, such structures are not yet commercially viable and pose integration challenges for practical applications. To overcome these limitations, we propose a new optical approach that enables control of the angular spread of light while the sensor is mechanically fixed. This method allows the sensor to remain fixed in position, simplifying the design and improving robustness. In this presentation, we introduce the concept of this angle-bandwidth change-based SPR spectroscopy system, a suitable sensor structure, and present experimental results demonstrating its feasibility and potential for low-cost, compact NIR sensing applications.

The dot product operator is a fundamental tool in various computational fields, particularly in photonic and edge computing applications. This paper explores the implementation and optimization of the dot product operator within photonic computing systems, leveraging the speed and energy efficiency of light-based processes. Two designs for a 4x4 dot product device were conceived, each with different input and output signal formats. The first design features an 8x3 pin configuration using Microring Resonators (MRRs) for computation. The second design utilizes Phase Change Material (PCM), which undergoes reversible phase transitions for non-volatile memory applications, enabling binary multiplication. Simulations conducted at a data rate of 30 Gbits/s, with a continuous wave laser input, confirmed the designs' performance, supported by graphical representations and truth tables comparing theoretical and simulated results. Our study highlights the potential of these designs to enhance machine learning, real-time signal processing, and advanced communication systems.

This paper presents simplified, high-speed all-optical logic gates using micro-ring resonators (MRRs) for photonic integrated circuits. Each logic gate consists of only two add-drop MRRs and passive waveguide routing, enabling basic logic operations such as AND/NOR, AND/NAND, and XOR/XNOR. A continuous wave (CW) light source is used as the output signal, while pump signals A and B serve as inputs to tune the resonance conditions of the MRRs. XOR and XNOR operations utilize a Mach–Zehnder Interferometer (MZI) combined with MRRs, whereas the other gates rely solely on resonant switching and routing through waveguides. The design eliminates the need for bandgap filters or optical isolators to separate the pump and CW signals, thereby reducing complexity and insertion loss. Thanks to the minimal component count and direct optical switching, the gates operate at speeds exceeding 20 Gbps, limited only by the intrinsic response time of the MRRs. This work offers a compact, CMOS-compatible platform for scalable, low-power, and high-speed all-optical computing applications.

Silicon nitride is a CMOS-compatible platform ideal for label-free optical biosensors; however, achieving efficient fiber-to-chip coupling typically requires large device footprints, which limit chip integration. This work presents a Mach-Zehnder interferometric biosensor integrated with a compact nonlinear inverse taper designed to address this challenge. The proposed coupler achieves a coupling efficiency of 99.28% within a total length of only 700 μm. This design yields a footprint reduction of 68.2% compared to conventional linear tapers, which require millimeter-scale lengths to achieve comparable performance. Furthermore, the biosensor uses an optimized rib waveguide geometry to maximize sensing performance. The sensing capability was validated through simulations of blood serum refractive index changes, in which the system demonstrates a sensitivity of 1630 nm/RIU and a limit of detection of 8.59×10^-5 RIU. These results highlight the potential of the proposed design as a compact, portable and sensitive lab-on-chip biosensing platform.

Silicon photonics (Si-Pho) is experiencing rapid advancements driven by demands for high-speed, low-power optical communication in data centers and emerging AI applications. Cavity as unique photonics feature was designed to reduce heat loss under Metal heater or optical loss under Edge coupler (EC). However, there are limited studies on cavity etching profile optimization. In this paper, different etch parameters are tested to simulate cavity etching profile on Lam SEMulator3D^®. SEMulator3D^® used here also helps to define more accurate residue-free cavity profile with its trade-off of depth requirement. Residue-free indicates adjacent cavity breakthrough, and depth control is to avoid top structure fracture. Here, different etched cavity profiles have been demonstrated by varying simulation parameters, such as ion angular sigma and lateral etching ratio, which could be realized by real plasma processing parameters (pressure, gas flow, bias power etc.). Specifically, SF6/O2 ratio was optimized in multiple steps of designed recipe. Also, time DOE was conducted to predict the depth target window with upper maximum CD.

We present a novel optical phased array (OPA) design employing two distinct wavelengths: a pump wavelength used to modulate the effective refractive index of the waveguides, and a signal wavelength used for beam steering. This all-optical, fully passive approach eliminates the need for active phase shifters or geometrical path-length engineering, such as waveguide bending, commonly used in conventional passive OPA designs. Beam steering is achieved by applying a spatially varying pump intensity across the waveguide array and monitoring the resulting far-field response at a fixed signal wavelength. By systematically adjusting the slope of the pump-intensity profile, we investigate its influence on far-field performance, demonstrating a scalable, low-complexity, and energy-efficient beam-steering solution. The proposed architecture is well suited for applications in free-space optical communication, light detection and ranging (LiDAR), and advanced imaging systems.

The increasing demand for mid-infrared photodetectors motivates the development of silicon-based devices compatible with CMOS technology. This study proposes a composite pyramid structure integrating upright and inverted pyramids to enhance localized surface plasma resonance and hot carrier generation. At the wavelength of 3.46 μm, the composite device achieves a responsivity of 17.37 μA/W, which is 266 times and 56 times higher than that of planar and inverted pyramid devices, respectively. The detection range is extended to the wavelength of 10 μm with a 75-fold improvement over the inverted pyramid structure. Numerical simulations reveal strong electric field confinement, confirming the effectiveness of the composite design for mid-infrared sensing applications.

To address the demand for more compact, multifunctional photonic components, we introduce a Combined Wavelength Demultiplexer / Splitter (CWDS) designed using adjoint-based topology optimization. We design the CWDS to separate signals at 1310 nm and 1550 nm, while equally dividing the optical powers between the designated two output ports designated for each wavelength. Measurements on fabricated devices, having small footprints of 6μm × 6μm, showed that our inversely designed CWDS achieved the desired wavelength separation and balanced power splitting. The measured splitting ratios for 1310 nm signals for 1550 nm signals were ±0.4 dB and ±0.1 dB, respectively. Also, the average channel-to-channel rejection ratios for 1550 nm signals measured in the 1310 nm window and for 1310 nm signals measured in the 1550 nm window were 14.6 dB and 24.2 dB, respectively.

Compact, low-loss Y-splitters are important components in integrated photonics for applications such as on-chip routing, sensing, and optical interconnects.^{1, 2} While inverse design has enabled ultra-compact splitters with excellent performance, understanding how specific geometry choices affect functionality remains limited.^{3, 4} This work investigates the role of mid-gap concave and convex geometries located at the inner vertices of the bifurcating, branching waveguides of Y-splitters that were designed using adjoint-based inverse-design. We show that applying a concave gap geometry consistently lowers insertion loss for various numbers of optimization points used in the design. In contrast, applying a convex gap geometry, although inspired by traditional adiabatic tapers,⁵ reduces performance and increases variability when the number of optimization points used is varied. We fabricated and measured an optimized Y-splitter with a concave gap geometry, designed using adjoint-based inverse-design, having a 1.6μm×1.2μm footprint, and achieved an ultra-low insertion loss of 0.039 dB. These findings highlight the importance of geometry-aware optimization and establish concave mid-region gap geometry as a key design feature for high-performance Y-splitters in photonic integrated circuits.

We present a compact and broadband graded-index multimode interferometer (MMI) implemented in silicon photonics using a slanted-rib geometry enabled by anisotropic KOH etching. The slanted sidewalls create a lateral variation in waveguide thickness, effectively engineering the modal dispersion to support broadband self-imaging. Finite-difference time domain (FDTD) simulations across the 1300–1600 nm range confirm low insertion loss and spectrally stable imaging. This fabrication-ready, CMOS compatible approach avoids complex lithography and provides a practical method for realizing graded-index structures in silicon. The proposed design offers a scalable platform for integrated broadband photonic components.

We present a mid-infrared silicon photonic sensor that simultaneously measures refractive index and absorption changes using a compact three-waveguide coupler acting as a modal interferometer. Variations in the surrounding medium modify both the real and imaginary components of the refractive index, introducing phase and amplitude imbalances between the input fields. These are converted into modal interference at the coupler, with the central port isolating the symmetric component for direct readout. Simulation results confirm a strong optical response, enabling compact and passive detection of environmental changes. Beyond sensing, the device is well-suited for coherent communication systems, where simultaneous monitoring of amplitude and phase fluctuations improves stability. Its inherent imbalance sensitivity also provides a diagnostic tool for identifying asymmetries and noise in integrated photonic circuits. This scalable design supports applications in environmental monitoring, industrial safety, coherent communications, imbalance detection, and lab-on-chip platforms.

Optically connected memory (OCM) architectures provide reconfigurable and high-bandwidth links for current data center applications. However, the continuously increasing computing demands on these applications, e.g., artificial intelligence and scientific computing, require efficient energy scaling in the order of 1 pJ/bit. In this work, an optimized carrier-depletion silicon modulator is proposed to demonstrate a PAM4 interconnect for an optically disaggregated memory architecture. We conduct an exploration of feasible multi-project wafer constraints for use in waveguide and carrier depletion design. Lastly, basic performance metrics for the OCM disaggregated link will be provided, namely, the number and type of devices, and the aggregated bandwidth.

This paper and poster, originally published on 4 March 2026, was replaced with a corrected/revised version on 18 March 2026. The spelling of Adrian Vilchez-Galvez's name has been corrected. If you downloaded the original PDFs but are unable to access the revisions, please contact SPIE Digital Library Customer Service for assistance. Download the erratum for additional details.